In traditional IC chips, aluminum, Al, and aluminum alloys have been used as interconnect metallurgies for providing electrical connections to and from devices in semiconductor interconnect (i.e., back-end-of-the-line, BEOL) layers of the devices. While Al-based metallurgies have been the material of choice for use as metal interconnects in the past, Al-based metallurgies no longer satisfy requirements as circuit density and speeds for IC chips increase and the scale of the devices decreases to nanometer dimensions. Thus, copper, Cu, and Cu-alloys are being employed as a replacement for Al-based metallurgies in nano-electronic devices because of their lower resistivity and their lower susceptibility to electromigration failure as compared to Al-based metallurgy.
One challenge relative to using Cu-based (i.e., pure Cu and Cu alloys) metallurgy is that it diffuses readily into the surrounding interconnect dielectric material as BEOL processing steps continue. To inhibit copper diffusion, copper-based interconnects can be isolated by employing protective barrier layers. Such protective barrier layers include, for example, conductive diffusion barrier liners of tantalum, titanium or tungsten, in pure, alloy and/or nitrided form, along the sidewalls and bottom of the copper-based interconnection. On the top surface of the copper-based interconnects, capping barriers are provided. In the prior art, such capping barrier layers comprise various dielectric materials, e.g., silicon nitride (Si3N4).
A conventional interconnect structure utilizing copper-based metallization and cap layers described above includes a lower substrate which may contain logic circuit elements such as, for example, transistors. An interlevel dielectric (ILD) layer is located above the substrate. The ILD layer may be formed of, for example, silicon dioxide (SiO2). However, in advanced interconnects, the ILD layer is preferably a low dielectric constant k material such as, for example, plasma deposited SiCOH or porous SiCOH. An adhesion promoter layer may be disposed between the substrate and the ILD layer. A silicon nitride (Si3N4) or SiCN (N-Blok) layer is optionally disposed on the ILD layer. The silicon nitride or silicon carbon nitride (N-Blok) layer is commonly known as a hard mask layer or polish stop layer. At least one conductor is embedded in the ILD layer. The conductor is typically copper or a copper alloy in advanced interconnects, but alternatively may be aluminum or another conductive material. When the conductor is copper-based, a diffusion barrier liner is preferably disposed between the ILD layer and the copper-based conductor. The diffusion barrier liner is typically comprised of tantalum, titanium, tungsten, or nitrides of these metals.
The top surface of the conductor is made coplanar with the top surface of the hard mask layer usually by a chemical-mechanical polish (CMP) step. A cap layer, also typically of silicon nitride or N-Blok, is disposed on the conductor and the hard mask layer. The cap layer acts as a diffusion barrier to prevent diffusion of copper from the conductor into the surrounding dielectric material during subsequent BEOL processing steps.
Plasma enhanced chemical vapor deposition (PECVD) films such as N-Blok or silicon nitride provide superior electromigration protection, and help to curtail diffusion of copper atoms along the interconnect surface.
Recently, the use of ultra low dielectric constant (ULK) dielectric materials (i.e. k<3.0) for copper-based interconnects have turned to ultra low k, two phase porous SiCOH. These dielectric materials require the use of a post-deposition curing step using ultraviolet (UV) and/or electron beam (E-Beam) radiation, for example. The energy used during post-deposition curing such as, for example, UV radiation, changes the cap film's stress to a more tensile direction. Typically, the energy of the curing process such as, for example, UV exposure, changes the stress of the cap layer from compressive to tensile which could potentially result in cracking and adhesion problems in both the cap layer and the ULK dielectric material, Any crack in the cap layer may lead to copper diffusion into the interconnect dielectric material layer, i.e., ILD, through the seam leading to formation of a copper nodule under the cap layer. The presence of such a copper nodule in the ILD may lead to short circuits due to leakage of current between adjacent interconnect lines.
The change from the cap film's compressive to tensile stress during the post-deposition curing treatment process will create intrinsic mechanically instability between the metal-cap-dielectric films and may also cause other damages such as, for example, increased cap-interlevel dielectric film cracking, delamination and blister formation over patterned copper lines, particularly during subsequent dielectric depositions, metallization, and chemical-mechanical polishing. Therefore, the retention of high compressive cap film's stress during post-deposition treatment is highly desirable for stable BEOL Cu-cap-low k ILD structures.
Furthermore, the need for reducing capacitance in advanced nano-electronic devices also requires that the overall dielectric constant of the cap film must be lower than silicon nitride (k˜7.0), silicon carbide (SiCH) and silicon carbon nitride (SiCNH, k˜5.5) cap films which are currently being employed in advanced interconnect structures.
In view of the foregoing, there is a need for a dielectric cap having a lower dielectric constant and higher mechanical and electrical stability to post-deposition curing treatment (e.g., UV and/or B-beam) than presently used dielectric cap materials.